Eugene Yip received his Bachelor of Engineering (Honours) with First Class Honours from The University of AucklandIn New Zealand. in May 2009. He received his PhDPhilosophiæ Doctor, supervised by Dr Partha Roop, Dr Morteza Biglari-Abhari, and Dr Alain Girault, in May 2016. In his PhD, he developed a novel deterministic parallel programming language (ForeC) and associated static timing analysis (ForeCast), suitable for designing safety-critical and mixed-critical multicore systems (ForeMC). He has served as a teaching assistant in the software design and digital logic courses, and a student mentoring scheme. His interests include real-time and mixed-critical systems, model-driven engineering, deterministic programming of embedded multicore systems, synchronous and logical execution time (LET) paradigms, static timing analysis, and automotive systems.
As a postdoc at the University of Auckland, he enabled the real-time testing of pacemaker devices by developing a realistic but computationally efficient model of the human heart. The heart's conduction system was modelled using hybrid automata and implemented in MatLab Simulink/Stateflow.
As a postdoc at the University of BambergGermany., he investigated the automated integration of software components that have time-sensitive communication protocols, the propagation of deadline misses across software components and its impact on system quality and reliability, and the compositional reasoning of Virtual Satellite designs being developed at the German Aerospace Center. He has served as a lecturer in the courses "reactive systems design" and "cyber-physical systems", as a supervisor of Bachelor's and Master's theses and projects, and as a teaching assistant in courses on software engineering, compiler construction, and applied software verification.
He has worked with Timing-ArchitectsCompany that specialised in the modelling, simulation, and analysis of automotive software timing behaviour., now part of Vector Informatik GmbH, to study the feasibility of modelling and simulating mixed-critical (time-triggered) logical execution time (LET) systems in their Tool Suite, to implement a Tool Suite plugin to demonstrate its feasibility, and to develop algorithms and heuristics that minimise LET communication overheads.
As a postdoc at the University of Bamberg, he was responsible for the planning, designing, prototyping, construction, configuration, and programming of digital model railway for teaching students important concepts in real-time, dependable, embedded systems. Staff and students have together developed a technology stack that includes a low-level communication library for the railway hardware, high-level server-client applications, and a domain-specific language for configuring and controlling railway systems. He has supervised and up-skilled staff and student assistants on construction methods, electronic circuit design, embedded programming, and the debugging of mechanical, electronic, and software issues.
Eugene is interested in website development and opensource projects. He has been involved in Velocity, formerly called Spark, which is a student-led organisation for fostering the spirit of entrepreneurship at the University of Auckland. He has also tried Salsa, Ceroc, and enjoys Ballroom dancing. To keep his writing fluid, he enjoys the use of fountain pens.
I was born in Hong Kong, grew up in Auckland, New Zealand, and now living in Bamberg, Germany. You may contact me by sending an email to eyip002@aucklanduni.ac.nz
__inline BOOL
SearchOneDirectory(
IN LPSTR Directory,
IN LPSTR FileToFind,
IN LPSTR SourceFullName,
IN LPSTR SourceFilePart,
OUT PBOOL FoundInTree
)
{
//
// This was way too slow. Just say we didn't find the file.
//
*FoundInTree = FALSE;
return(TRUE);
}
Note: This was found in the 2004 leaked Windows sources.
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